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Description: 大容量存储器，Nandflash控制的VHDL实现代码，经验证时序正常，器件可以正常工作。-Large-capacity memory, Nandflash control VHDL implementation code, proven normal sequence, the device is working properly.
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Size: 7168 |
Author: 画生 |
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Description: vhdl fliflops Logic elements that process memory - circuits that retain their output even
though their inputs change - are introduced. These single-bit logic elements,
called flip-flops or latches, are available in various types. Those examined are:
D flip-flops
JK flip-flops
SR latches
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Size: 161792 |
Author: sagar |
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Description: 波形存储器的设计，利用文件中VHDL可以加载一定的波形数据，文件包含可直接运行的仿真图-Waveform memory design using VHDL file can load some of the waveform data files contain simulation can be run directly Figure
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Size: 344064 |
Author: chaoshui |
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Description: 随 机 存 储 器（SRAM）的 vhdl 源 代 码-Static random access memory (SRAM) in vhdl source code
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Size: 345088 |
Author: Liwag |
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Description: 用VHDL语言设计一个8位双向可控移位寄存器。
移位寄存器由D型触发器构成，采用串入并出形式。
采用VHDL方式设计一个16х4位RAM存储器-VHDL language to design an 8-bit bidirectional shift register controllable. The shift register by a D-type flip-flops, using the string into and out of form. Way design using VHDL a bit RAM memory 16х4
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Size: 1024 |
Author: 赵丽丽 |
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Description: This file is about create memory in ISE by VHDL language.
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Size: 11264 |
Author: najme.yousefi |
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Description: How to create a RAM memory in VHDL
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Size: 330752 |
Author: jose |
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Description: this file contain a simple example of a memory eeprom using vhdl
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Size: 2853888 |
Author: paco |
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Description: this is a VHDL code for content address memory
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Size: 177152 |
Author: divya |
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Description: This project has dependencies in the 'digilent' VHDL library. For your convenience
a local copy of these dependencies are included in the remote_sources directory.
The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup.
The project configures the two cameras on the VmodCAM for maximum resolution
and frame rate, RGB output and video snapshot mode. The DDR memory on-board
the Atlys is used as a frame buffer. The two video feeds from both cameras are
bufferd in the DDR, while the FPGA drives the HDMI out port with either of the
cameras. Switch 7 selects the camera which gets displayed. The resolution of
the cameras (1600x1200) gets cropped to fit the display resolution of 1600x900.
Project built in ISE 13.2, tested in ISE 13.1.
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Size: 13762560 |
Author: domnish |
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Description: 计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。(The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. )
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Size: 7415808 |
Author: 马晨 |
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